1. Field of the Invention
The present invention relates generally to a verification system and method for a design under test, and particularly to such a system and method utilizing constrained random test parameter selection for providing substantially complete design verification more efficiently.
2. Description of the Related Art
Today's application specific integrated circuit (ASIC) designs have become increasingly complex, as they have followed Moore's Law. Moore's Law states that the number of transistors that will fit on an integrated circuit chip will double every eighteen months. This has primarily been driven by advances in circuit fabrication technology, such as optical lithography techniques. For example, ASIC designs in the year 2000 were seen to target 180 nm feature size and were on the order of several hundred thousand gates. In 2010, current designs target the 40 nm feature sizes and are on the order of several million gates. However, empirical data shows that as design complexity has increased, so has the likelihood of chip re-spins. The majority of chip re-spins has been seen to be due to the existence of a programming bug in a digital logic function of the chip which causes the chip to fail to operate correctly and/or produce an incorrect or unintended result. Digital logic functions, such as functions that may appear in an ASIC, are typically defined in source code using a Hardware Description Language (HDL).
With chip complexity increasing, the time for verifying a chip design has played a more prominent role in the development cycle of the chip. Traditionally, directed tests, in which individual functions are exercised using individual test cases, sufficed to completely verify a design, but now, as complexity has increased, more sophisticated testing methods are required.
Directed tests are useful to ensure that the design's basic modes operate as intended and so they are usually the first test cases created. They will point out gross functional bugs, but each only covers a single state or combination of the design parameters. Each design parameter has a valid range that must be tested along with all combinations of the other parameters' ranges to ensure functionality of the design across all scenarios.
Random selection of a design's test parameters frees the verifier from hand-creating each possible test in a directed fashion. However, each variable may have a limited range of valid values, and often each parameter is not independent, so only certain combinations of parameter values may be valid. For these reasons, constrained random (or directed random) methodologies were developed. Constrained random testing is an approach that can increase functional test coverage more efficiently than directed test creation. It also has the benefit of uncovering corner cases, i.e., those situations outside the normal operating conditions of a device, which the verification engineer would not have otherwise conceived.
SystemVerilog, which is an HDL that is based on contributions from several EDA companies, is unique in that it offers both design and verification constructs within a single language. SystemVerilog extends the syntax of the Verilog HDL with additional constructs to support constrained random verification. In particular, SystemVerilog introduces the rand variable type, the constraint, and coverpoint syntax. A rand variable is one for which a random value may be chosen at each simulation invocation. A constraint directs the choice of a random variable's value based on logical conditions. Coverpoints record the selection of these random variables, as well as special combinations of these variables, to record functional coverage. In this manner, test parameters are “randomly” chosen, but within practical constraints established by the coder. This frees the verification engineer from specifically creating directed tests for every possible combination of the random variables, but also avoids invalid combinations that need not be tested. Though the use of constrained random verification in SystemVerilog has been found to be very helpful to a system designer, there are inefficiencies therein that result in a less optimal amount of time needed for testing a chip.